The present invention relates to an amplifier for a switched capacitor amplifier circuit.
Switched capacitor circuits are used as amplifiers in numerous applications. One example is a use in a pipeline analog/digital converter 10 as illustrated in FIG. 1A. FIG. 1A shows an amplifier configuration having an amplifier circuit. The amplifier configuration is designed with a switched capacitor Cf, Cs and is also referred to below as a switched capacitor amplifier circuit. An example of an application in reset configuration is shown here. Problems due to an offset of an amplifier V used therein may be bypassed by using this configuration, because this offset is saved in a first clock phase Φ1 of two clock phases Φ1, Φ2 and no longer appears as an error in a second clock phase Φ2.
An input voltage Vi is applied on input line i, leads to a first switch S1 and a second switch S2 connected parallel thereto. These two switches S1, S2 are triggerable for closing by a first switching signal, which is applied in a first clock phase Φ1. The second switchable capacitor Cs is connected in series between the first switch S1 and an amplifier input node n of the amplifier V. Furthermore, the first switchable capacitor Cf is connected between the second switch S2 and the amplifier input node n. A negative input of amplifier V is connected between amplifier input node n and a circuit output or amplifier output node o. An output voltage Vo is provided at the amplifier output node o. A positive input of the amplifier V is connected to a reference potential GND or to a ground terminal.
The amplifier input node n is connectable in parallel to the amplifier output node o via a third switch S3. For switching and closing the third switch S3, a first switching signal Φ1 may also be applied thereto. Furthermore, a control voltage in the form of a digital/analog converter output voltage Vdac or another reference potential, such as a reference voltage Vcm, may be applied to a node between the first switch S1 and the second switchable capacitor Cs via a fifth switch S5. A second switching signal, which is applied in second clock phase Φ2, switches and closes the fifth switch S5. A node between the second switch S2 and the first switchable capacitor Cf is switchable together with amplifier output node o via a fourth switch S4, which is also triggered to close by the second switching signal.
A control unit X, provides the first and second switching signals, among other things, in first and second clock phase Φ1, Φ2. Triggering is performed in a known manner.
During first clock phase Φ1, as shown in FIG. 2, the capacitors or their capacitances CS and CF are connected in parallel and are connected to the circuit input i via the first two switches S1 and S2 shown in FIG. 1A. The amplifier V has complete feedback via the third switch S3. The output voltage Vo, and thus the voltage at the second node of the two capacitors Cs and Cf, is reference voltage Vcm, also referred to as common mode voltage, plus offset voltage Voff of the amplifier V. The difference between the input voltage Vi and the sum of offset voltage Voff and reference voltage Vcm is stored on the parallel circuit of the first two capacitors CS and CF.
During second clock phase Φ2, as shown in FIG. 3, the first two switches S1 and S2 shown in FIG. 1A are opened. The fifth switch S5 is closed and connects the second switchable capacitor Cs to reference voltage Vcm in the case of a switched capacitor amplifier circuit or a digital/analog converter output voltage Vdac in the case of a pipeline analog/digital converter. At the same time, the complete feedback loop of the amplifier V is cancelled, because the third switch S3 is opened, and the first switchable capacitor Cf is connected by the closed fourth switch S4 from amplifier input node n of amplifier V to its output node o. This yields the following value as the output voltage of the amplifier V in second clock phase Φ2:Vo(Φ1)=Vi−(Vcm+Voff)and
            V      o        ⁡          (              Φ        ⁢                                  ⁢        2            )        =                              Cs          +          Cf                Cf            ·              Vi        ⁡                  (                      Φ            ⁢                                                  ⁢            1                    )                      =          Gain      ·                        Vi          ⁡                      (                          Φ              ⁢                                                          ⁢              1                        )                          .            
Output voltage Vo in the second clock phase Φ2 is thus the amplified negative input voltage Vi in the first clock phase Φ1, which compensates for the offset voltage Voff. The gain=1+(Cs/Cf) of the configuration as a whole is:
  Gain  =                    Cf        +        Cs            Cf        =          1      +                        Cs          Cf                .            This equation is known to be accurate only when a gain A0 of the amplifier V has an infinitely large value. At a finite value of gain A0, the output voltage is wrong by the value of an amplifier error Aerr.
  Gain  ,          ⁢      real    =                                        Cf            +            Cs                    Cf                ·                  1                      1            +                                          1                /                A                            ⁢                                                          ⁢              0                                          =                                                  Cf              +              Cs                        Cf                    ·          A                ⁢                                  ⁢        e        ⁢                                  ⁢        r        ⁢                                  ⁢                  r          .                    Amplifier error Aerr becomes smaller, the greater the gain A0 of the amplifier V. To reduce the error in the gain A0, single-stage amplifier configurations, so-called OTA circuits, i.e., transconductance amplifiers or an operational amplifier having current-controlled gain, are used, for example, in the amplifier V in combination with cascode circuits. The gain A0 may be further increased by using so-called gain boosting circuits. The advantage of the single-stage configurations is that high bandwidths are achieved, because no additional measures for frequency compensation are necessary.
However, the use of cascode circuits is hardly possible in applications having low power supply voltages. In this situation, multistage amplifier configurations are used to achieve the highest possible gain A0. The reduction in the gain A0 due to the lack of cascode configuration is that additional measures must be taken for frequency compensation to ensure stable systems according to the regulating technology. FIG. 6 shows a possible two-stage gain configuration of an amplifier 600 having frequency compensation.
The amplifier 600 includes an upstream amplifier stage V1 and amplifier stage V2, having gradients gm1 and gm2, respectively, connected in series between amplifier input node n and amplifier output node o. Between the two amplifier stages V1, V2 there is a node, which is referred to below as compensation input node n2. A first amplifier capacitor C1 and the first additional resistor Ro1 are connected in parallel between reference potential GND or the ground terminal and compensation input nodes n2. Furthermore, a load capacitance CL and a second additional resistor Ro2 are connected in parallel between reference potential GND or the ground terminal and amplifier output node o.
In a practical implementation, in particular the first amplifier capacitor C1 and the first additional resistor Ro1 are already formed by component properties. The first additional resistor Ro1 is the output resistor of upstream amplifier stage V1 as the source of the real gradient gm1, the first amplifier capacitor C1 is the input capacitor of the second amplifier stage V2 with its gradient gm2 and the parasitic load capacitance of the output of upstream amplifier stage V1. There need not, but may be, an explicit placement of the first additional resistor Ro1 or the first amplifier capacitor C1. Accordingly, any parasitic elements present, if necessary, are sufficient.
A first compensation resistor RZ and a capacitor or a total capacitance for frequency compensation CC are connected in parallel to the second of the amplifier stages V2 and in series between the compensation input nodes n2 and the amplifier output nodes o.
A problem with the switched capacitor amplifier circuit 10 illustrated in FIG. 1 and the amplifier 600 illustrated in FIG. 6 is that feedback factor 13 of the amplifier 600 is different in the two clock phases Φ1 and Φ2:β(Φ1)≠β(Φ2).During the first clock phase Φ1, amplifier 600 has complete feedback. The feedback factor β(Φ1) is then:β(Φ1)=1.
However, during the second clock phase Φ2, the amplifier 600 has only a smaller amount of feedback. The feedback factor β(Φ2) is then less than 1 and amounts to:
      β    ⁡          (              Φ        ⁢                                  ⁢        2            )        =            Cf              Cf        +        Cs              =                  1                  1          +                      Cs            /            Cf                              .      For a classical 1.5-bit pipeline analog/digital converter, it holds that Cf=Cs, and thus feedback factor β(Φ2) is equal to ½ during the second clock phase Φ2.
A frequency compensation for multi-stage amplifiers is to be designed to obtain a stable system according to regulating technology in both clock phases Φ1, Φ2. Due to the greater feedback factor β(Φ1) during the first clock phase Φ1, this phase is the crucial phase for the frequency compensation.
FIG. 6 illustrates a possible frequency compensation for a second-order gain system, a so-called Miller compensation. For a feedback factor β of β=1 and with a given load capacitance CL, a certain transit frequency fT is obtained with selected gradients gm1 and gm2 of the two amplifier stages V1, V2, as is known from, e.g., P. E. Allan, D. R. Holberg; CMOS Analog Circuit Design; Oxford University Press; 1987; ISBN 0-19-510720-9; page 374ff; section 8.2, etc. This transit frequency fT is equal to a gain-bandwidth product GBW of the amplifier 600, and with a feedback factor β of β=1, it is equal to the −3 dB bandwidth of feedback amplifier V* with fT=f−3 dB Gain(Φ1) of operational amplifier OPV:GBW=A0·f−3 dB OPV for β=1→GBW=fT=gm1/2πCC.→f−3 dB Gain(Φ1)=fT·β(Φ1)=gm1/2πCC.During the second clock phase Φ2, the feedback factor β is much lower under some circumstances. In the case of a pipeline analog/digital converter stage having a gain A0=2, the feedback factor β is only ½. However, since gain-bandwidth product GBW is constant and must be designed for the first clock phase Φ1, the resulting −3 dB bandwidth of the feedback amplifier 600 with fT=f−3 dB Gain(Φ2) is:
                    ⁢                  G        ⁢                                  ⁢        B        ⁢                                  ⁢        W            =              A        ⁢                                  ⁢                  0          ·                      f                                          -                3                            ⁢                                                          ⁢              dB              ⁢                                                          ⁢              OPV                                                      for      ⁢                          ⁢      β        =                  1        ->                  G          ⁢                                          ⁢          B          ⁢                                          ⁢          W                    =              fT        =                                                                              g                                      m                    ⁢                                                                                  ⁢                    1                                                  /                2                            ⁢                                                          ⁢              π              ⁢                                                          ⁢                              C                C                                      ->                                          f                                                      -                    3                                    ⁢                                                                          ⁢                  dB                  ⁢                                                                          ⁢                  Gain                                            ⁡                              (                                  Φ                  ⁢                                                                          ⁢                  2                                )                                              =                                    fT              ·                              β                ⁡                                  (                  Φ2                  )                                                      =                                                            g                                      m                    ⁢                                                                                  ⁢                    1                                                  /                                  (                                      2                    ×                    2                    ⁢                                                                                  ⁢                    π                    ⁢                                                                                  ⁢                                          C                      C                                                        )                                            =                                                1                  2                                ·                                                                            f                                                                        -                          3                                                ⁢                                                                                                  ⁢                        dB                        ⁢                                                                                                  ⁢                        Gain                                                              ⁡                                          (                                              Φ                        ⁢                                                                                                  ⁢                        1                                            )                                                        .                                                                        
The bandwidth of the feedback amplifier 600 during the second clock phase Φ2 is thus only half as large as during first clock phase Φ1. This results in a longer transient recovery time, which is to be avoided only by a greater bandwidth in the first clock phase Φ1 and thus by a higher power consumption. FIG. 7 shows a frequency response of the open-loop as well as the resulting frequency response of the feedback circuit, for β=1 during the first clock phase Φ1, as well as for β=½ during the second clock phase Φ2.
There is a need for an amplifier and a switched capacitor amplifier circuit with an improved circuit design.